power consumption analysis

Figure 3. Full-adder design using Domino circuit (24 transistors)

In the above designs, the size of each NMOS transistor is W/L=3μm/2μm, the size of each PMOS transistor is W/L=9μm/2μm. Power sources are: Vdd=5V, Gnd=0V. In PSPICE, you also need to consider the connections of bulk terminal of each transistor. (1). (4’) Briefly explain the working principle of the Domino full adder. (2). (10’) Based on the designs shown in Figure 2 and 3, list the expressions of outputs Co and S implemented in both CMOS and Domino full adders separately. Use Boolean logic to prove that they are the same as Equation (1) and (2) for one bit full adder. (That is, you first list the expressions of outputs Co and S implemented in Figure 2 and 3, and then prove that they are equivalent to Equations (1) and (2).) (3). (40’) Use PSPICE Capture to design the schematic of CMOS full adder shown in Figure 2. Then perform transient simulation to simulate its output response for 4 input patterns. Denote the input patterns ABCi=”000, 001, 010, 011, 100, 101, 110, 111” as pattern #0, 1, 2, 3, 4, 5, 6, 7 separately. Please use the last 4 digits of the student ID of one student in your group as your input pattern sequence, each number in your student ID stands for the corresponding input pattern number. The number “8” and “9” in your student ID corresponds to pattern #0. For example, if the last four digits of your student ID is 3279, then input pattern sequence: “#3, #2, #7, #0”, which is: ABCi=011, 010, 111, 000. Each pattern lasts for 200ns. Print out the screen shot of your schematic design, and the waveforms of all the input/output signals (A, B, Ci, Co, S, etc.). Based on your simulated waveforms, fill Table 1. (4). (40’) Use PSPICE Capture to design the schematic of dynamic domino adder shown in Figure 3. Then perform transient simulation to simulate its output response. Use the same input patterns as you used in step (3) for CMOS adder. The precharge and evaluation phases for each pattern last for 100ns and 100ns separately. That is, clock period Tclk=200ns. Please print out the screen shot of your schematic design, and the waveforms of all the input/output signals (A, B, Ci, Co, S, clock Φ, etc.). Based on your simulated waveforms, fill in Table 2. (5). (1’) Compare the output response of CMOS and Domino full adders in evaluation phase (Φ=1). Are they the same as each other?

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(6). (5’) Submit a detailed project report for this project. In your report, you need to briefly introduce what you have done in this project, what tools you used, and what conclusions you have made. For each figure (e.g. screenshot of schematic design, simulation waveforms, etc.), you need to give a caption and brief explain the figure in your report (e.g. what do you observe from this figure? What’s the meaning of each waveform? Are the simulated waveforms in good agreement with the expectation or not? What conclusion can you draw from this simulation result?). Please don’t leave any figure without explanations. In a word, you need to make your project report easily understandable by others who are not familiar with your project. You may need to show your project reports to a company when you want to find a job in VLSI industry in the future. Please use attached SPICE model file for PSPICE simulation. Save your design files in your USB drive and do not delete them. You will need to perform power consumption analysis on them in your next project. This is a group project. Two students act as a group, with one student doing the CMOS full adder design, and another student doing the Domino full adder design. Both students submit a joint report, and answer all the questions in this project. Please use only one student’s ID for deciding the test patterns for both designs. In your report, please clearly identify who did the CMOS design and who did the Domino design. Both students should collaborate with each other in the group project. If you wish to do the project all by yourself without partner, it is allowed but no extra credit will be given for doing the project alone. Due: 02/19/2018, Monday in class.

Table 1. Simulation results of designed CMOS full adder (My student ID:_____________) Pattern A B Ci Expected

Co Simulated

Co Agreement?

(Yes/No) Expected

S Simulated

S Agreement?

(Yes/No) #1 #2 #3 #4

Table 2. Simulation results of designed Domino full adder (My student ID:_____________)

Pattern A B Ci Φ Expected Co

Simulated Co

Agreement? (Yes/No)

Expected S

Simulated S

Agreement? (Yes/No)

#1 0 1

#2 0 1

#3 0 1

#4 0 1