Effect of parasitic capacitance


Computer Engineering

EGCP 441 – 02 – Advanced Electronics for Computer Engineering

(Spring 2017) Lab No 6: Interconnect Modeling Using Cad

Laboratory Goals

 Understanding of Interconnection

 Effect of parasitic capacitance

 Spice netlist

 Transient analysis using Hspice or Tspice

Pre-lab / lab reading

 Course Textbook (Chapter no 6)

 Lecture slides no 15

1. Output Resistance using Hspice For the inverter shown in Figure 1 measure the Rout using the Hspice. Compared the

measured results with the hand calculations. For hand calculation assume for 0.5um

technology, VDD=2.5 V, K’n=100 uA/V 2 , Vtn=0.4 V, λn=0.1 V

-1 , (W/L)n=10, K’p=60 uA/V

2 ,

Vtp=-0.4V, λp=0.2 V -1

, (W/L)p=17

 Write the netlist for the circuit shown in Figure 1

 Connect a load capacitance of 100 fF

 Measure the propagation delay tPLH using Hspice.

 Using tp = 0.69 x Rout x Cout

 Calculate the propagation delay (𝑡𝑝 = 𝑡𝑝𝑙ℎ+𝑡𝑝ℎ𝑙

2 ) using average current technique.

Figure 1 CMOS inverter circuit

 Then equate the propagation delay to a simple RC network and find Rout.

2. Delay Measurement using Hspice An interconnection modeling of an interconnection network is shown in Figure 2. Use the

spice netlist given with the lab to model the interconnection network.

For the interconnection network shown in Figure 2 measure the delay at node no 5 using


 Write the netlist for the interconnection network shown in Figure 2

 Use Elmore technique to compute the time constant and LH propagation delay (tPLH)

of the above network from the gate input to node 5.

3. Analysis

Write a brief summary report for the lab. Be sure to also include the following topics:

Include the schematic for Figure 1 and Figure 2. A netlist for part 1 and part 2. Also include

the transient response for part 1 and part 2.

Show each calculation steps. Compare your simulation result your hand calculation. If there

is any difference then list down the possible reason behind it.

Explain any difficulties you had with these labs. (Please include any suggestions to improve


Figure 2 RC interconnection modelling